cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 1/6 MTNK3C3 cystek product specification esd protected n-channel mosfet MTNK3C3 description ? low voltage drive, 1.8v. ? easy to use in parallel. ? high speed switching. ? esd protected device. ? pb-free package. symbol outline absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage bv dss 20 v gate-source voltage v gs 8 v continuous drain current i d 100 ma pulsed drain current i dm 400 *1 ma total power dissipation p d 150 *2 mw esd susceptibility 350 *3 v operating junction and storage temperature range tj -55~+150 c thermal resistance, junction-to-ambient rth,ja 833 c/w note : *1. pulse width 300 s, duty cycle 2%. *2. when device mounted on recommended land pattern. *3. human body model, 1.5k in series with 100pf. sot-523 bv dss 20v i d 100ma r dson 3 d g MTNK3C3 g gate s source d drain s
cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 2/6 MTNK3C3 cystek product specification electrical characteristics (ta=25 c) symbol min. typ. max. unit test conditions static bv dss 20 - - v v gs =0, i d =100 a v gs(th) 0.5 - 1.0 v v ds =v gs , i d =250 a i gss - - 1 a v gs = 8v, v ds =0 i dss - - 500 na v ds =20v, v gs =0 - 1.7 3 v gs =4.5v, i d =100ma r ds(on) - 3.5 6 v gs =1.8v, i d =20ma g fs 100 - - ms v ds =5v, i d =100ma dynamic c iss - 23 50 c oss - 7.7 25 c rss - 5.8 5 pf v ds =10v, v gs =0, f=1mhz source-drain diode *v sd - - 1 v v gs =0v, i s =10ma *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping marking MTNK3C3 sot-523 (pb-free) 3000 pcs / tape & reel k3
cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 3/6 MTNK3C3 cystek product specification typical characteristics typical output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 01234 drain-source voltage -vds(v) drain current - id(a) vgs=1.5v 3.5v 4.5v 3v 1.8v 2.0v 2.5v 5v 4.0v typical transfer characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0123456 gate-source voltage-vgs(v) drain current -id(a) vds=3v static drain-source on-state resistance vs drain current 1 10 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance-rds(on)() vgs=1.8v vgs=4.5v static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 6 7 024681 gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() 0 id=100ma id=20ma reverse drain current vs source-drain voltage 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 00.10.20.3 reverse drain current -idr(a) source-drain voltage-vsd(v) 0.4 capacitance vs drain-to-source voltage 1 10 100 0.1 1 10 100 drain-source voltage -vds(v) capacitance---(pf) ciss c oss crss
cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 4/6 MTNK3C3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 5/6 MTNK3C3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c447c3 issued date : 2011.09.19 revised date : page no. : 6/6 MTNK3C3 cystek product specification sot-523 dimension *: typical n h f 12 3 j a b c d e g i k l m o style: pin 1.gate 2.source 3.drain 3-lead sot-523 plastic surface mounted package cystek package code: c3 marking: k3 date code device code inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0079 0.0157 0.20 0.40 i *0.0197 - *0.50 - b 0.0591 0.0669 1.50 1.70 j 0.0610 0.0650 1.55 1.65 c 0.0118 0.0197 0.30 0.50 k 0.0276 0.0315 0.70 0.80 d 0.0295 0.0335 0.75 0.85 l 0.0224 0.0248 0.57 0.63 e 0.0118 0.0197 0.30 0.50 m 0.0020 0.0059 0.05 0.15 f 0.0039 0.0118 0.10 0.30 n 0.0039 0.0118 0.10 0.30 g 0.0039 0.0118 0.10 0.30 o 0 0.0031 0 0.08 h *0.0197 - *0.50 - notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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